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M25PE80
8 Mbit, low-voltage, Page-Erasable Serial Flash memory with Byte alterability, 50MHz SPI bus, standard pinout
Feature summary

Industrial Standard SPI Pin-out 8 Mbits of Page-Erasable Flash Memory Page Write (up to 256 Bytes) in 11ms (typical) Page Program (up to 256 Bytes) in 1.35ms (typical) Page Erase (256 Bytes) in 10ms (typical) Sector Erase (512 Kbits) Bulk Erase (8 Mbits) 2.7 to 3.6V Single Supply Voltage SPI Bus Compatible Serial Interface 50MHz Clock Rate (maximum) Deep Power-down Mode 1A (typical) Electronic Signature - JEDEC Standard Two-Byte Signature (8014h) More than 100,000 Write Cycles More than 20 Year Data Retention Hardware Write Protection of the Top Sector (64KB) Software Write Protection on a 64KByte Sector Basis Software Write Protection on a 4KByte Subsector Basis for Sector 0 and Sector 15 Packages - ECOPACK(R) (RoHS compliant) SO8W (MW) 208 mils width VFQFPN8 (MP) 6 x 5mm (MLP8)

May 2006
Rev 4
1/51
www.st.com 1
Contents
M25PE80
Contents
1 2 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 2.2 2.3 2.4 2.5 2.6 Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Reset (Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Top Sector Lock (TSL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 4
SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 Sharing the overhead of modifying data . . . . . . . . . . . . . . . . . . . . . . . . . . 11 An easy way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 A fast way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . . 12 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Active Power, Standby Power and Deep Power-Down modes . . . . . . . . . 12 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5 6
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.1 6.2 6.3 6.4 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.4.1 6.4.2 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.5
Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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M25PE80
Contents
6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15
Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . 25 Read Lock Register (RDLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Page Write (PW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Write to Lock Register (WRLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Page Erase (PE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Deep Power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Release from Deep Power-down (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7 8 9 10 11 12 13
Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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List of tables
M25PE80
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Software protection truth table (Sectors 1 to 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Software protection scheme truth table (Sectors 0 and 15) . . . . . . . . . . . . . . . . . . . . . . . . 15 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Read Identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Lock Register Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Lock Register In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Power-Up timing and VWI threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Reset timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 VFQFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead, 6x5mm, Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 SO8 wide - 8 lead Plastic Small Outline, 208 mils body width, mechanical data. . . . . . . . 48 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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M25PE80
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 VFQFPN and SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Software protection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Write Enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Read Identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 22 Read Status Register (RDSR) instruction sequence and data-out sequence . . . . . . . . . . 23 Read Data Bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 24 Read Data Bytes at Higher Speed (FAST_READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Read Lock Register (RDLR) instruction sequence and data-out Sequence. . . . . . . . . . . . 27 Page Write (PW) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Page Program (PP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Write to Lock Register (WRLR) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Page Erase (PE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Sector Erase (SE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 bulk erase (be) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Deep Power-down (DP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Release from Deep Power-down (RDP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . 38 Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Top Sector Lock setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Reset AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 VFQFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead, 6x5mm, Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 SO8 wide - 8 lead Plastic Small Outline, 208 mils body width, Package Outline. . . . . . . . 48
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Summary description
M25PE80
1
Summary description
The M25PE80 is an 8 Mbit (1Mb x 8) Serial Paged Flash Memory accessed by a high speed SPI-compatible bus. The memory can be written or programmed 1 to 256 Bytes at a time, using the Page Write or Page Program instruction. The Page Write instruction consists of an integrated Page Erase cycle followed by a Page Program cycle. The memory is organized as 16 sectors, each containing 256 pages. Each page is 256 Bytes wide. Thus, the whole memory can be viewed as consisting of 4096 pages, or 1,048,576 Bytes. The memory can be erased a page at a time, using the Page Erase instruction, a sector at a time, using the Sector Erase instruction, or as a whole, using the Bulk Erase instruction. The memory can be Write Protected by either Hardware or Software, with a protection granularity of either 64 KBytes (sector granularity) or 4 KBytes (sub-sector granularity inside sector 0 and sector 15 only). In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. ECOPACK(R) packages are Lead-free and RoHS compliant. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 1. Logic diagram
VCC
D C S TSL Reset M25PE80
Q
VSS
AI10779
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M25PE80 Table 1.
C D Q S TSL Reset VCC VSS
Summary description Signal names
Serial Clock Serial Data Input Serial Data Output Chip Select Top Sector Lock Reset Supply Voltage Ground
Figure 2.
VFQFPN and SO connections
M25PE80 S Q TSL VSS 1 2 3 4 8 7 6 5 VCC Reset C D
AI10780
1. There is an exposed die paddle on the underside of the MLP8 package. This is pulled, internally, to VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB. 2. See Package mechanical section for package dimensions, and how to identify pin-1.
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Signal description
M25PE80
2
2.1
Signal description
Serial Data Output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C).
2.2
Serial Data Input (D)
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (C).
2.3
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
2.4
Chip Select (S)
When this input signal is High, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Read, Program, Erase or Write cycle is in progress, the device will be in the Standby mode (this is not the Deep Power-down mode). Driving Chip Select (S) Low selects the device, placing it in the Active Power mode. After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction.
2.5
Reset (Reset)
The Reset (Reset) input provides a hardware reset for the memory. When Reset (Reset) is driven High, the memory is in the normal operating mode. When Reset (Reset) is driven Low, the memory will enter the Reset mode. In this mode, the output is high impedance. Driving Reset (Reset) Low while an internal operation is in progress will affect this operation (write, program or erase cycle) and data may be lost.
2.6
Top Sector Lock (TSL)
This input signal puts the device in the Hardware Protected mode, when Top Sector Lock (TSL) is connected to VSS, causing the top 256 pages (upper addresses) of the memory to become read-only (protected from write, program and erase operations). When Top Sector Lock (TSL) is connected to VCC, the top 256 pages of memory behave like the other pages of memory.
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M25PE80
SPI modes
3
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes:

CPOL=0, CPHA=0 CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 4, is the clock polarity when the bus master is in Stand-by mode and not transferring data:

C remains at 0 for (CPOL=0, CPHA=0) C remains at 1 for (CPOL=1, CPHA=1) Bus master and memory devices on the SPI bus
SDO SPI Interface with (CPOL, CPHA) = (0, 0) or (1, 1) SDI SCK CQD Bus Master (ST6, ST7, ST9, ST10, Others) SPI Memory Device CS3 CS2 CS1 S TSL RP S TSL RP S TSL RP SPI Memory Device SPI Memory Device CQD CQD
Figure 3.
AI10741
1. The Top Sector Lock (TSL) signal should be driven, High or Low as appropriate.
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SPI modes Figure 4.
CPOL CPHA C
M25PE80 SPI modes supported
0
0
1
1
C
D
MSB
Q
MSB
AI01438B
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M25PE80
Operating features
4
4.1
Operating features
Sharing the overhead of modifying data
To write or program one (or more) data Bytes, two instructions are required: Write Enable (WREN), which is one Byte, and a Page Write (PW) or Page Program (PP) sequence, which consists of four Bytes plus data. This is followed by the internal cycle (of duration tPW or tPP). To share this overhead, the Page Write (PW) or Page Program (PP) instruction allows up to 256 Bytes to be programmed (changing bits from 1 to 0) or written (changing bits to 0 or 1) at a time, provided that they lie in consecutive addresses on the same page of memory.
4.2
An easy way to modify data
The Page Write (PW) instruction provides a convenient way of modifying data (up to 256 contiguous Bytes at a time), and simply requires the start address, and the new data in the instruction sequence. The Page Write (PW) instruction is entered by driving Chip Select (S) Low, and then transmitting the instruction Byte, three address Bytes (A23-A0) and at least one data Byte, and then driving Chip Select (S) High. While Chip Select (S) is being held Low, the data Bytes are written to the data buffer, starting at the address given in the third address Byte (A7-A0). When Chip Select (S) is driven High, the Write cycle starts. The remaining, unchanged, Bytes of the data buffer are automatically loaded with the values of the corresponding Bytes of the addressed memory page. The addressed memory page then automatically put into an Erase cycle. Finally, the addressed memory page is programmed with the contents of the data buffer. All of this buffer management is handled internally, and is transparent to the user. The user is given the facility of being able to alter the contents of the memory on a Byte-by-Byte basis. For optimized timings, it is recommended to use the Page Write (PW) instruction to write all consecutive targeted Bytes in a single sequence versus using several Page Write (PW) sequences with each containing only a few Bytes (see Page Write (PW) section and Table 16., AC Characteristics).
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Operating features
M25PE80
4.3
A fast way to modify data
The Page Program (PP) instruction provides a fast way of modifying data (up to 256 contiguous Bytes at a time), provided that it only involves resetting bits to 0 that had previously been set to 1. This might be:

when the designer is programming the device for the first time when the designer knows that the page has already been erased by an earlier Page Erase (PE), Sector Erase (SE) or Bulk Erase (BE) instruction. This is useful, for example, when storing a fast stream of data, having first performed the erase cycle when time was available when the designer knows that the only changes involve resetting bits to 0 that are still set to 1. When this method is possible, it has the additional advantage of minimising the number of unnecessary erase operations, and the extra stress incurred by each page
For optimized timings, it is recommended to use the Page Program (PP) instruction to program all consecutive targeted Bytes in a single sequence versus using several Page Program (PP) sequences with each containing only a few Bytes (see Page Program (PP) section and Table 16: AC Characteristics).
4.4
Polling during a Write, Program or Erase cycle
A further improvement in the write, program or erase time can be achieved by not waiting for the worst case delay (tPW, tPP, tPE, tSE or tBE). The Write In Progress (WIP) bit is provided in the Status Register so that the application program can monitor its value, polling it to establish when the previous cycle is complete.
4.5
Reset
An internal Power-On Reset circuit helps protect against inadvertent data writes. Addition protection is provided by driving Reset (RESET) Low during the Power-on process, and only driving it High when VCC has reached the correct voltage level, VCC(min).
4.6
Active Power, Standby Power and Deep Power-Down modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode. When Chip Select (S) is High, the device is deselected, but could remain in the Active Power mode until all internal cycles have completed (Program, Erase, Write). The device then goes in to the Standby Power mode. The device consumption drops to ICC1. The Deep Power-down mode is entered when the specific instruction (the Deep Powerdown (DP) instruction) is executed. The device consumption drops further to ICC2. When in this mode, only the Release from Deep Power-down instruction is accepted. All other instructions are ignored. The device remains in the Deep Power-down mode until the Release from Deep Power-down instruction is executed. This can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent Write, Program or Erase instructions.
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M25PE80
Operating features
4.7
Status Register
The Status Register contains two status bits that can be read by the Read Status Register (RDSR) instruction. See Section 6.4: Read Status Register (RDSR) for a detailed description of the Status Register bits.
4.8
Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25PE80 features the following data protection mechanisms:

Power On Reset and an internal timer (tPUW) can provide protection against inadvertant changes while the power supply is outside the operating specification. Program, Erase and Write instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: - - - - - - - - - Power-up Reset (RESET) driven Low Write Disable (WRDI) instruction completion Page Write (PW) instruction completion Page Program (PP) instruction completion Write to Lock Register (WRLR) instruction completion Page Erase (PE) instruction completion Sector Erase (SE) instruction completion Bulk Erase (BE) instruction completion
The Hardware Protected mode is entered when Top Sector Lock (TSL) is driven Low, causing the top 256 pages of memory to become read-only. When Top Sector Lock (TSL) is driven High, the top 256 pages of memory behave like the other pages of memory. The Reset (Reset) signal can be driven Low to protect the contents of the memory during any critical time, not just during Power-up and Power-down. In addition to the low power consumption feature, the Deep Power-down mode offers extra software protection from inadvertant Write, Program and Erase instructions while the device is not in active use. The Software Protection is managed by specific Lock Registers assigned to each sector and sub-sector as follows: - - Each 64KB sector has a Lock Register. Inside sector 0 and sector 15, each 4KB sub-sector also has a Lock Register (in addition to the Lock Register at sector level).

The Lock Registers can be read and written using the Read Lock Register (RDLR) and Write to Lock Register (WRLR) instructions. In each Lock Register two bits control the protection of each sector/sub-sector: the Write Lock Bit and the Lock Down Bit.
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Operating features - Write Lock Bit:
M25PE80
The Write Lock Bit determines whether the contents of the sector/sub-sector can be modified (using the Write, Program or Erase instructions). When the Write Lock Bit is set, `1', the sector/sub-sector is write protected - any operations that attempt to change the data in the sector/sub-sector will fail. When the Write Lock Bit is reset to `0', the sector/sub-sector is not write protected by the Lock Register, and may be modified, unless TSL is Low (in which case the top sector will remain write protected). - Lock Down Bit: The Lock Down Bit provides a mechanism for protecting software data from simple hacking and malicious attack. When the Lock Down Bit is set, `1', further modification to the Write Lock and Lock Down Bits cannot be performed. A reset, or power-up, is required before changes to these bits can be made. When the Lock Down Bit is reset, `0', the Write Lock and Lock Down Bits can be changed. The Write Lock Bit and the Lock Down Bit are volatile and their value is reset to `0' after a Power-Down or a Reset. The definition of the Lock Register bits is given in Table 8: Lock Register Out. Refer to Table 2 and Table 3 for details on the Software Protection for sectors 1 to 14 and 0 and 15, respectively. Figure 5 shows the the Software Protection scheme. Table 2. Software protection truth table (Sectors 1 to 14)
Protection Status
Sector Lock Register Lock Down Bit 0 0 Write Lock Bit 0 1
Sector Unprotected from Program/Erase/Write operations, Protection Status Reversible Sector Protected from Program/Erase/Write operations, Protection Status Reversible Sector Unprotected from Program/Erase/Write operations, Sector Protection Status cannot be changed except by a Reset or Powerup. Sector Protected from Program/Erase/Write operations, Sector Protection Status cannot be changed except by a Reset or Powerup.
1
0
1
1
14/51
M25PE80 Table 3.
Sector Lock Register
Operating features Software protection scheme truth table (Sectors 0 and 15)(1) (2)
Sub-Sector Lock Register Protection Status Lock Write Lock Write Down Lock Down Lock Bit Bit Bit Bit 0 0 Current Sub-Sector Unprotected from Program/Erase/Write operations, Current Sub-Sector Protection Status Reversible Current Sub-Sector Protected from Program/Erase/Write operations, Current Sub-Sector Protection Status Reversible. Current Sub-Sector Unprotected from Program/Erase/Write operations, Current Sub-Sector Protection Status cannot be changed except by a Reset or Power-up. Current Sub-Sector Protected from Program/Erase/Write operations, Current Sub-Sector Protection Status cannot be changed except by a Reset or Power-up. All Sub-Sectors Protected from Program/Erase/Write operations, Current Sub-Sector Protection Status Reversible All Sub-Sectors Protected from Program/Erase/Write operations, Current Sub-sector Protection Status cannot be changed except by a Reset or Power-up. Current Sub-Sector Unprotected from Program/Erase/Write operations, All Sub-sectors Protection Status cannot be changed except by a Reset or Power-up Current Sub-Sector Protected from Program/Erase/Write operations, All Sub-sectors Protection Status cannot be changed except by a Reset or Power-up All Sub-sectors Protected with their Protection Status cannot be changed except by a Reset or Power-up.
0 0 1 0 1
1
0
1
0 1 1
1
1
1 0 1 1
0
1
1
1
1
1. All other bit combinations are not-applicable. 2. For more details, refer to the description of the Write to Lock Register (WRLR) instruction.
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Operating features Figure 5. Software protection scheme
Sub-Sector 15.15 Lock Register Sub-Sector 15.15 (4KB) Sub-Sector Modify Protected LD bit SECTOR 15 WL bit
M25PE80
SECTOR 15 LOCK REGISTER Sub-Sector 15.15 Lock Register Frozen Sub-Sector 15.0 Lock Register Sub-Sector Modify Protected LD bit WL bit All Sub-Sectors Modify Protected LD bit WL bit
Sub-Sector 15.0 (4KB)
All Sub-Sector Lock Registers Frozen
SECTOR 14 (64KBx 14)
Sub-Sector 15.0 Lock Register Frozen SECTOR LOCK REGISTER 14 Sector Modify Protected LD bit WL bit
Sector Lock Register Frozen
SECTOR LOCK REGISTER 1 Sector Modify Protected LD bit SECTOR 1 (64KBx 14) WL bit
Sector Lock Register Frozen Sub-Sector 0.15 Lock Register
Sub-Sector 0.15 (4KB)
Sub-Sector Modify Protected LD bit WL bit SECTOR 0 LOCK REGISTER
SECTOR 0
Sub-Sector 0.15 Lock Register Frozen Sub-Sector 0.0 Lock Register Sub-Sector Modify Protected LD bit WL bit
All Sub-Sectors Modify Protected LD bit WL bit
Sub-Sector 0.0 (4KB)
All Sub-Sector Lock Registers Frozen
Sub-Sector 0.0 Lock Register Frozen
AI11305a
1. LD Lock Down bit; WL Write Lock bit.
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M25PE80
Memory organization
5
Memory organization
The memory is organized as:

4096 pages (256 Bytes each). 1,048,576 Bytes (8 bits each) 16 sectors (512 Kbits, 65536 Bytes each) programmed (bits are programmed from 1 to 0) erased (bits are erased from 0 to 1) written (bits are changed to either 0 or 1)
Each page can be individually:

The device is Page, Sector or Bulk Erasable (bits are erased from 0 to 1). Table 4. Memory organization
Sector 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 F0000h E0000h D0000h C0000h B0000h A0000h 90000h 80000h 70000h 60000h 50000h 40000h 30000h 20000h 10000h 00000h Address Range FFFFFh EFFFFh DFFFFh CFFFFh BFFFFh AFFFFh 9FFFFh 8FFFFh 7FFFFh 6FFFFh 5FFFFh 4FFFFh 3FFFFh 2FFFFh 1FFFFh 0FFFFh
17/51
Memory organization Figure 6.
Reset TSL S C D Q Control Logic High Voltage Generator
M25PE80 Block Diagram
I/O Shift Register
Address Register and Counter
256 Byte Data Buffer
Status Register
FFFFFh F0000h Top 256 Pages can be made read-only by using the TSL pin
Y Decoder
Whole Memory Array can be made read-only on a 64KB or 4KB basis through the Lock Registers
00000h 256 Bytes (Page Size) X Decoder
000FFh
AI10782c
18/51
M25PE80
Instructions
6
Instructions
All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select (S) is driven Low. Then, the one-Byte instruction code must be shifted in to the device, most significant bit first, on Serial Data Input (D), each bit being latched on the rising edges of Serial Clock (C). The instruction set is listed in Table 5. Every instruction sequence starts with a one-Byte instruction code. Depending on the instruction, this might be followed by address Bytes, or by data Bytes, or by both or none. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read), Read Identification (RDID), Read Status Register (RDSR), or Read Lock Register (RDLR) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (S) can be driven High after any bit of the data-out sequence is being shifted out. In the case of a Page Write (PW), Page Program (PP), Write to Lock Register (WRLR), Page Erase (PE), Sector Erase (SE), Bulk Erase (BE), Write Enable (WREN), Write Disable (WRDI), Deep Power-down (DP) or Release from Deep Power-down (RDP) instruction, Chip Select (S) must be driven High exactly at a Byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (S) must driven High when the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write cycle, Program cycle or Erase cycle are ignored, and the internal Write cycle, Program cycle or Erase cycle continues unaffected.
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Instructions Table 5.
Instruction WREN WRDI RDID RDSR WRLR RDLR READ FAST_READ PW PP PE SE BE DP RDP
M25PE80 Instruction set
Description Write Enable Write Disable Read Identification Read Status Register Write to Lock Register Read Lock Register Read Data Bytes Read Data Bytes at Higher Speed Page Write Page Program Page Erase Sector Erase Bulk Erase Deep Power-down Release from Deep Power-down One-Byte Instruction Code 0000 0110 0000 0100 1001 1111 0000 0101 1110 0101 1110 1000 0000 0011 0000 1011 0000 1010 0000 0010 1101 1011 1101 1000 1100 0111 1011 1001 1010 1011 06h 04h 9Fh 05h E5h E8h 03h 0Bh 0Ah 02h DBh D8h C7h B9h ABh Address Dummy Bytes Bytes 0 0 0 0 3 3 3 3 3 3 3 3 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Data Bytes 0 0 1 to 3 1 to 1 1 1 to 1 to 1 to 256 1 to 256 0 0 0 0 0
6.1
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 7) sets the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Write (PW), Page Program (PP), Page Erase (PE), Sector Erase (SE), Bulk Erase (BE) and Write to Lock Register (WRLR) instructions. The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. Figure 7. Write Enable (WREN) instruction sequence
S 0 C Instruction D High Impedance Q
AI02281E
1
2
3
4
5
6
7
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M25PE80
Instructions
6.2
Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 8) resets the Write Enable Latch (WEL) bit. The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. The Write Enable Latch (WEL) bit is reset under the following conditions:

Power-up Write Disable (WRDI) instruction completion Page Write (PW) instruction completion Page Program (PP) instruction completion Write to Lock Register (WRLR) instruction completion Page Erase (PE) instruction completion Sector Erase (SE) instruction completion Bulk Erase (BE) instruction completion Write Disable (WRDI) instruction sequence
S 0 C Instruction D High Impedance Q
AI03750D
Figure 8.
1
2
3
4
5
6
7
21/51
Instructions
M25PE80
6.3
Read Identification (RDID)
The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be read, followed by two Bytes of device identification. The manufacturer identification is assigned by JEDEC, and has the value 20h for STMicroelectronics. The device identification is assigned by the device manufacturer, and indicates the memory type in the first Byte (80h), and the memory capacity of the device in the second Byte (14h). Any Read Identification (RDID) instruction while an Erase or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code for the instruction is shifted in. This is followed by the 24-bit device identification, stored in the memory, being shifted out on Serial Data Output (Q), each bit being shifted out during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 9. The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at any time during data output. When Chip Select (S) is driven High, the device is put in the Stand-by Power mode. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. Table 6. Read Identification (RDID) data-out sequence
Device Identification Manufacturer Identification Memory Type 20h 80h Memory Capacity 14h
Figure 9.
Read Identification (RDID) instruction sequence and data-out sequence
S 0 C Instruction D Manufacturer Identification High Impedance Q MSB 15 14 13 MSB
AI06809b
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
28 29 30 31
Device Identification 3 2 1 0
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M25PE80
Instructions
6.4
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Program, Erase or Write cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in Figure 10. The status bits of the Status Register are as follows:
6.4.1
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress.
6.4.2
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write, Program or Erase instruction is accepted. Table 7.
b7 0 0 0 0 0 0 WEL
(1)
Status Register format
b0 WIP(1)
1. WEL and WIP are volatile read-only bits (WEL is set and reset by specific instructions; WIP is automatically set and reset by the internal logic of the device).
Figure 10. Read Status Register (RDSR) instruction sequence and data-out sequence
S 0 C Instruction D Status Register Out High Impedance Q 7 MSB 6 5 4 3 2 1 0 7 MSB
AI02031E
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Status Register Out 6 5 4 3 2 1 0 7
23/51
Instructions
M25PE80
6.5
Read Data Bytes (READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-Byte address (A23-A0), each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, is shifted out on Serial Data Output (Q), each bit being shifted out, at a maximum frequency fR, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 11. The first Byte addressed can be at any location. The address is automatically incremented to the next higher address after each Byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any Read Data Bytes (READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 11. Read Data Bytes (READ) instruction sequence and data-out sequence
S 0 C Instruction 24-Bit Address 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
D High Impedance Q
23 22 21 MSB
3
2
1
0 Data Out 1 7 6 5 4 3 2 1 0 Data Out 2 7
MSB
AI03748D
1. Address bits A23 to A20 are Don't Care.
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M25PE80
Instructions
6.6
Read Data Bytes at Higher Speed (FAST_READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-Byte address (A23A0) and a dummy Byte, each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, is shifted out on Serial Data Output (Q), each bit being shifted out, at a maximum frequency fC, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 12. The first Byte addressed can be at any location. The address is automatically incremented to the next higher address after each Byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 12. Read Data Bytes at Higher Speed (FAST_READ) instruction sequence and data-out sequence
S 0 C Instruction 24 BIT ADDRESS 1 2 3 4 5 6 7 8 9 10 28 29 30 31
D High Impedance Q
23 22 21
3
2
1
0
S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Dummy Byte
D
7
6
5
4
3
2
1
0 DATA OUT 1 DATA OUT 2 1 0 7 MSB 6 5 4 3 2 1 0 7 MSB
AI04006
Q
7 MSB
6
5
4
3
2
1. Address bits A23 to A20 are Don't Care.
25/51
Instructions
M25PE80
6.7
Read Lock Register (RDLR)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Lock Register (RDLR) instruction is followed by a 3-Byte address (A23-A0) pointing to any location inside the concerned sector (or sub-sector). Each address bit is latched-in during the rising edge of Serial Clock (C). Then the value of the Lock Register is shifted out on Serial Data Output (Q), each bit being shifted out, at a maximum frequency fC, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 13. The Read Lock Register (RDLR) instruction is terminated by driving Chip Select (S) High at any time during data output. Any Read Lock Register (RDLR) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Table 8.
Bit b7-b4 `1' b3 Sub-sector Lock Down(1) `0' `1' b2 Sub-sector Write Lock(1) `0'
Lock Register Out
Bit Name Value Reserved The Write Lock and Lock Down Bits cannot be changed Once a `1' is written to the Lock Down Bit it cannot be cleared to `0' except by a Reset or power-up. The Write Lock and Lock Down Bits can be changed by writing new values to them. (Default value). Write, Program and Erase operations in this sub-sector will not be executed. The memory contents will not be changed. Write, Program and Erase operations in this sub-sector are executed and will modify the sub-sector contents. (Default value). The Write Lock and Lock Down Bits cannot be changed. Once a `1' is written to the Lock Down Bit it cannot be cleared to `0', except by a Reset or power-up. The Write Lock and Lock Down Bits can be changed by writing new values to them. (Default value). Write, Program and Erase operations in this sector will not be executed. The memory contents will not be changed. Write, Program and Erase operations in this sector are executed and will modify the sector contents. (Default value). Function
`1' b1 Sector Lock Down `0' `1' b0 Sector Write Lock `0'
1. Valid only for sector 0 and sector 15 (the value `0' is returned for other sectors).
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M25PE80
Instructions Figure 13. Read Lock Register (RDLR) instruction sequence and data-out Sequence
S 0 C Instruction 24-Bit Address 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
D High Impedance Q
23 22 21 MSB
3
2
1
0 Lock Register Out 7 6 5 4 3 2 1 0
MSB
AI10783
27/51
Instructions
M25PE80
6.8
Page Write (PW)
The Page Write (PW) instruction allows Bytes to be written in the memory. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Page Write (PW) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, three address Bytes and at least one data Byte on Serial Data Input (D). The rest of the page remains unchanged if no power failure occurs during this write cycle. The Page Write (PW) instruction performs a page erase cycle even if only one Byte is updated. If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data exceeding the addressed page boundary roll over, and are written from the start address of the same page (the one whose 8 least significant address bits (A7-A0) are all zero). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 14. If more than 256 Bytes are sent to the device, previously latched data are discarded and the last 256 data Bytes are guaranteed to be written correctly within the same page. If less than 256 Data Bytes are sent to device, they are correctly written at the requested addresses without having any effects on the other Bytes of the same page. For optimized timings, it is recommended to use the Page Write (PW) instruction to write all consecutive targeted Bytes in a single sequence versus using several Page Write (PW) sequences with each containing only a few Bytes. Chip Select (S) must be driven High after the eighth bit of the last data Byte has been latched in, otherwise the Page Write (PW) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Page Write cycle (whose duration is tPW) is initiated. While the Page Write cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Write cycle, and is 0 when it is completed. At some unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is reset. A Page Write (PW) instruction applied to a page that is Hardware or Software Protected is not executed. Any Page Write (PW) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
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M25PE80 Figure 14. Page Write (PW) instruction sequence
S 0 C Instruction 24-Bit Address Data Byte 1 1 2 3 4 5 6 7 8 9 10
Instructions
28 29 30 31 32 33 34 35 36 37 38 39
D
23 22 21 MSB
3
2
1
0
7
6
5
4
3
2
1
0
MSB
S 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 C Data Byte 2 Data Byte 3 Data Byte n
D
7
6
5
4
3
2
1
0
7 MSB
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
AI04045
1. Address bits A23 to A20 are Don't Care 2. 1 n 256
29/51
Instructions
M25PE80
6.9
Page Program (PP)
The Page Program (PP) instruction allows Bytes to be programmed in the memory (changing bits from 1 to 0, only). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, three address Bytes and at least one data Byte on Serial Data Input (D). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data exceeding the addressed page boundary roll over, and are programmed from the start address of the same page (the one whose 8 least significant address bits (A7-A0) are all zero). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 15. If more than 256 Bytes are sent to the device, previously latched data are discarded and the last 256 data Bytes are guaranteed to be programmed correctly within the same page. If less than 256 Data Bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other Bytes of the same page. For optimized timings, it is recommended to use the Page Program (PP) instruction to program all consecutive targeted Bytes in a single sequence versus using several Page Program (PP) sequences with each containing only a few Bytes (see Table 16: AC Characteristics). Chip Select (S) must be driven High after the eighth bit of the last data Byte has been latched in, otherwise the Page Program (PP) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) instruction applied to a page that is Hardware or software Protected is not executed. Any Page Program (PP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
30/51
M25PE80 Figure 15. Page Program (PP) instruction sequence
S 0 C Instruction 24-Bit Address Data Byte 1 1 2 3 4 5 6 7 8 9 10
Instructions
28 29 30 31 32 33 34 35 36 37 38 39
D
23 22 21 MSB
3
2
1
0
7
6
5
4
3
2
1
0
MSB
S 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 C Data Byte 2 Data Byte 3 Data Byte n
D
7
6
5
4
3
2
1
0
7 MSB
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
MSB
AI04044
1. Address bits A23 to A20 are Don't Care 2. 1 n 256
31/51
Instructions
M25PE80
6.10
Write to Lock Register (WRLR)
The Write to Lock Register (WRLR) instruction allows bits to be changed in the Lock Registers. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Write to Lock Register (WRLR) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, three address Bytes (pointing to any address in the targeted sector/sub-sector) and one data Byte on Serial Data Input (D). The instruction sequence is shown in Figure 16. Chip Select (S) must be driven High after the eighth bit of the data Byte has been latched in, otherwise the Write to Lock Register (WRLR) instruction is not executed. When the Write to Lock Register (WRLR) instruction has been successfully executed, the Write Enable Latch (WEL) bit is reset after a delay time less than tSHSL minimum value. Any Write to Lock Register (WRLR) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 16. Write to Lock Register (WRLR) instruction sequence
S 0 C Instruction 24-Bit Address Lock Register In 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
D
23 22 21 MSB
3
2
1
0
7
6
5
4
3
2
1
0
MSB
AI10784
32/51
M25PE80 Table 9. Lock Register In
Sector All Sectors Except for Sector 0 and Sector 15 Bit b7-b2 b1 b0 Value `0' Sector Lock Down Bit Value (refer to Table 8) Sector Write Lock Bit Value (refer to Table 8) `1' b7 `0' Sector 0 Sector 15 b3 b2 b1 b0
1. b6-b4 and b1-b0 must be reset to `0'. 2. b6-b2 must be reset to `0'.
Instructions
Only b3 and b2 are taken into account to modify the sub-sector Write Lock and Lock Down bits(1) Only b1 and b0 are taken into account to modify the sector Write Lock and Lock Down bits(2)
Sub-sector Lock Down Bit value (refer to Table 8) Sub-sector Write Lock Bit Value (refer to Table 8) Sector Lock Down Bit Value (refer to Table 8) Sector Write Lock Bit Value (refer to Table 8)
Protection always prevails:
When the Lock Down Bit of Sector 0 or Sector 15 is set to `1'. - - If the Lock Down Bit of Sector 0 is `1', all the Lock Down Bits of the sub-sectors in Sector 0 are forced to `1'. If the Lock Down Bit of Sector 15 is `1', all the Lock Down Bits of the sub-sectors in Sector 15 are forced to `1' if the Write Lock Bit of Sector 0 is `1', the Write Lock Bits of all the sub-sectors in Sector 0 are forced to `1' (even if their Lock Down Bits are set to `1'). if the Write Lock Bit of Sector 15 is `1', the Write Lock Bits of all the sub-sectors in Sector 15 are forced to `1' (even if their Lock Down Bits are set to `1'). if the Write Lock Bit of Sector 0 is `0', all the sub-sectors in Sector 0 whose Lock Down Bit is `0' have their Write Lock Bits forced to `0'. if the Write Lock Bit of Sector 15 is `0', all the sub-sectors in Sector 15 whose Lock Down Bit is `0' have their Write Lock Bits forced to `0'.
When the Write Lock Bit of Sector 0 or Sector 15 is set to `1'. - -
When the Write Lock Bit of Sector 0 or Sector 15 is reset to `0'. - -
When the Write Lock Bit of any sector or sub-sector is set to `1', any instruction that may modify the contents of this sector or sub-sector will be rejected (including Sector Erase and Bulk Erase).
Note that when the WRLR instruction acts both on Write Lock (WL) and Lock Down (LD) bits, it firstly programs the WL bit, and then the LD bit. As an example, if a sub-sector Lock Register settings are xxxx0101b and a WRLR instruction is issued with a Lock Register In data set to 00000010b:
1. the sector WL bit is first set to `0' (and all sub-sectors that are not locked-down will have their WL bit reset to `0'). 2. the sector LD bit and all sub-sectors LD bits are set to `1'.
In this case, the final value of the above sub-sector Lock Register is xxxx1010b.
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Instructions
M25PE80
6.11
Page Erase (PE)
The Page Erase (PE) instruction sets to 1 (FFh) all bits inside the chosen page. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Page Erase (PE) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, and three address Bytes on Serial Data Input (D). Any address inside the Page is a valid address for the Page Erase (PE) instruction. Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 17. Chip Select (S) must be driven High after the eighth bit of the last address Byte has been latched in, otherwise the Page Erase (PE) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Page Erase cycle (whose duration is tPE) is initiated. While the Page Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the selftimed Page Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is reset. A Page Erase (PE) instruction applied to a page that is Hardware or software Protected is not executed. Any Page Erase (PE) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 17. Page Erase (PE) instruction sequence
S 0 C Instruction 24 Bit Address 1 2 3 4 5 6 7 8 9 29 30 31
D
23 22 MSB
2
1
0
AI04046
1. Address bits A23 to A20 are Don't Care.
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M25PE80
Instructions
6.12
Sector Erase (SE)
The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Sector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, and three address Bytes on Serial Data Input (D). Any address inside the Sector (see Table 4) is a valid address for the Sector Erase (SE) instruction. Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 18. Chip Select (S) must be driven High after the eighth bit of the last address Byte has been latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) instruction applied to a sector that contains a page that is Hardware or software Protected is not executed. Any Sector Erase (SE) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 18. Sector Erase (SE) instruction sequence
S 0 C Instruction 24 Bit Address 1 2 3 4 5 6 7 8 9 29 30 31
D
23 22 MSB
2
1
0
AI03751D
1. Address bits A23 to A20 are Don't Care.
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Instructions
M25PE80
6.13
Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 19. Chip Select (S) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Bulk Erase cycle (whose duration is tBE) is initiated. While the Bulk Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. Any Bulk Erase (BE) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. A Bulk Erase (BE) instruction is ignored if at least one sector or sub-sector is write-protected (Hardware or Software protection). Figure 19. bulk erase (be) Instruction Sequence
S 0 C Instruction D 1 2 3 4 5 6 7
AI03752D
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M25PE80
Instructions
6.14
Deep Power-down (DP)
Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all Write, Program and Erase instructions. Driving Chip Select (S) High deselects the device, and puts the device in the Standby mode (if there is no internal cycle currently in progress). But this mode is not the Deep Powerdown mode. The Deep Power-down mode can only be entered by executing the Deep Power-down (DP) instruction, subsequently reducing the standby current (from ICC1 to ICC2, as specified in Table 15). Once the device has entered the Deep Power-down mode, all instructions are ignored except the Release from Deep Power-down (RDP) instruction. Issuing the Release from Deep Power-down (RDP) instruction will cause the device to exit the Deep Power-down mode. The Deep Power-down mode automatically stops at Power-down, and the device always Powers-up in the Standby mode. The Deep Power-down (DP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 20. Chip Select (S) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as Chip Select (S) is driven High, it requires a delay of tDP before the supply current is reduced to ICC2 and the Deep Power-down mode is entered. Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 20. Deep Power-down (DP) instruction sequence
S 0 C Instruction D 1 2 3 4 5 6 7 tDP
Stand-by Mode
Deep Power-down Mode
AI03753D
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Instructions
M25PE80
6.15
Release from Deep Power-down (RDP)
Once the device has entered the Deep Power-down mode, all instructions are ignored except the Release from Deep Power-down (RDP) instruction. Executing this instruction takes the device out of the Deep Power-down mode. The Release from Deep Power-down (RDP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 21. The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (S) High. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is driven Low, cause the instruction to be rejected, and not executed. After Chip Select (S) has been driven High, followed by a delay, tRDP, the device is put in the Standby mode. Chip Select (S) must remain High at least until this period is over. The device waits to be selected, so that it can receive, decode and execute instructions. Any Release from Deep Power-down (RDP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 21. Release from Deep Power-down (RDP) instruction sequence
S 0 C Instruction D 1 2 3 4 5 6 7 tRDP
High Impedance Q Deep Power-down Mode Stand-by Mode
AI06807
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M25PE80
Power-up and Power-down
7
Power-up and Power-down
At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied on VCC) until VCC reaches the correct value:

VCC(min) at Power-up, and then for a further delay of tVSL VSS at Power-down
Usually a simple pull-up resistor on Chip Select (S) can be used to ensure safe and proper Power-up and Power-down. To avoid data corruption and inadvertent write operations during power-up, a Power On Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less than the Power On Reset (POR) threshold voltage, VWI - all operations are disabled, and the device does not respond to any instruction. Moreover, the device ignores all Write Enable (WREN), Page Write (PW), Page Program (PP), Page Erase (PE), Sector Erase (SE), Bulk Erase (BE) and Write to Lock Register (WRLR) instructions until a time delay of tPUW has elapsed after the moment that VCC rises above the VWI threshold. However, the correct operation of the device is not guaranteed if, by this time, VCC is still below VCC(min). No Write, Program or Erase instructions should be sent until the later of:

tPUW after VCC passed the VWI threshold tVSL after VCC passed the VCC(min) level
These values are specified in Table 10. If the delay, tVSL, has elapsed, after VCC has risen above VCC(min), the device can be selected for READ instructions even if the tPUW delay is not yet fully elapsed. As an extra protection, the Reset (Reset) signal could be driven Low for the whole duration of the Power-up and Power-down phases.
At Power-up, the device is in the following state:

The device is in the Standby mode (not the Deep Power-down mode). The Write Enable Latch (WEL) bit is reset.
Normal precautions must be taken for supply rail decoupling, to stabilize the VCC supply. Each device in a system should have the VCC rail decoupled by a suitable capacitor close to the package pins. (Generally, this capacitor is of the order of 0.1F). At Power-down, when VCC drops from the operating voltage, to below the Power On Reset (POR) threshold voltage, VWI, all operations are disabled and the device does not respond to any instruction. (The designer needs to be aware that if a Power-down occurs while a Write, Program or Erase cycle is in progress, some data corruption can result.)
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Power-up and Power-down Figure 22. Power-up timing
VCC VCC(max) Program, Erase and Write Commands are Rejected by the Device Chip Selection Not Allowed VCC(min) Reset State of the Device VWI tPUW tVSL Read Access allowed
M25PE80
Device fully accessible
time
AI04009C
Table 10.
Symbol tVSL(1) tPUW(1) VWI(1)
Power-Up timing and VWI threshold
Parameter VCC(min) to S low Time delay before the first Write, Program or Erase instruction Write Inhibit Voltage Min. 30 1 1.5 10 2.5 Max. Unit s ms V
1. These parameters are characterized only, over the temperature range -40C to +85C.
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M25PE80
Initial delivery state
8
Initial delivery state
The device is delivered with the memory array erased: all bits are set to 1 (each Byte contains FFh). All usable Status Register bits are 0.
9
Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 11.
Symbol TSTG VIO VCC VESD Storage Temperature Input and Output Voltage (with respect to Ground) Supply Voltage Electrostatic Discharge Voltage (Human Body model)(1)
Absolute maximum ratings
Parameter Min. -65 -0.6 -0.6 -2000 Max. 150 4.0 4.0 2000 Unit C V V V
1. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 , R2=500 ).
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DC and AC parameters
M25PE80
10
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measurement Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 12.
Symbol VCC TA Supply Voltage Ambient Operating Temperature
Operating conditions
Parameter Min. 2.7 -40 Max. 3.6 85 Unit V C
Table 13.
Symbol CL
AC measurement conditions
Parameter Load Capacitance Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Reference Voltages Min. 30 5 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC Max. Unit pF ns V V
1. Output Hi-Z is defined as the point where data out is no longer driven.
Figure 23. AC measurement I/O waveform
Input Levels 0.8VCC Input and Output Timing Reference Levels 0.7VCC 0.3VCC
AI00825B
0.2VCC
Table 14.
Symbol COUT CIN
Capacitance
Parameter Output Capacitance (Q) Input Capacitance (other pins) Test Condition VOUT = 0V VIN = 0V Min. Max. 8 6 Unit pF pF
1. Sampled only, not 100% tested, at TA=25C and a frequency of 20 MHz.
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M25PE80 Table 15.
Symbol ILI ILO ICC1 ICC2 ICC3 ICC4 ICC5 VIL VIH VOL VOH
DC and AC parameters DC Characteristics
Parameter Input Leakage Current Output Leakage Current Standby Current (Standby and Reset modes) Deep Power-down Current Operating Current (FAST_READ) Operating Current (PW) Operating Current (SE) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 1.6 mA IOH = -100A VCC-0.2 S = VCC, VIN = VSS or VCC S = VCC, VIN = VSS or VCC C = 0.1VCC / 0.9.VCC at 50MHz, Q = open S = VCC S = VCC - 0.5 0.7VCC Test Condition (in addition to those in Table 12) Min. Max. 2 2 50 10 8 15 15 0.3VCC VCC+0.4 0.4 Unit A A A A mA mA mA V V V V
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DC and AC parameters Table 16. AC Characteristics
Test conditions specified in Table 12 and Table 13 Symbol Alt. Parameter Clock Frequency for the following instructions: FAST_READ, RDLR, PW, PP, WRLR, PE, SE, DP, RDP, WREN, WRDI, RDSR Clock Frequency for READ instructions tCLH tCLL Clock High Time Clock Low Time Clock Slew Rate tSLCH tCHSL tDVCH tCHDX tCHSH tSHCH tSHSL tSHQZ(2) tCLQV tCLQX tTHSL tSHTL tDP
(2) (2)
M25PE80
Min.
Typ.
Max.
Unit
fC
fC
D.C.
50
MHz
fR tCH(1) tCL(1)
D.C. 9 9
20
MHz ns ns V/ns ns ns ns ns ns ns ns
(peak to peak)
0.1 5 5 2 5 5 5 100 8 8 0 50 100 3 30 11 10.1 + n * 0.9/256 1.35 0.45 + n * 0.9/256 10 1 10 5 25
tCSS
S Active Setup Time (relative to C) S Not Active Hold Time (relative to C)
tDSU tDH
Data In Setup Time Data In Hold Time S Active Hold Time (relative to C) S Not Active Setup Time (relative to C)
tCSH tDIS tV tHO
S Deselect Time Output Disable Time Clock Low to Output Valid Output Hold Time Top Sector Lock Setup Time Top Sector Lock Hold Time S to Deep Power-down S High to Standby Mode Page Write Cycle Time (256 Bytes)
ns ns ns ns ns s s ms
tRDP(2) tPW(3)
Page Write Cycle Time (n Bytes) Page Program Cycle Time (256 Bytes)
tPP(3) tPE tSE tBE
ms
Page Program Cycle Time (n Bytes) Page Erase Cycle Time Sector Erase Cycle Time Bulk Erase Cycle Time
20 5 60
ms s s
1. tCH + tCL must be greater than or equal to 1/ fC 2. Value guaranteed by characterization, not 100% tested in production. 3. When using PP and PW instructions to update consecutive Bytes, optimized timings are obtained with one sequence including all the Bytes versus several sequences of only a few Bytes (1 n 256).
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M25PE80 Figure 24. Serial input timing
DC and AC parameters
tSHSL S tCHSL C tDVCH tCHDX D MSB IN tCLCH LSB IN tCHCL tSLCH tCHSH tSHCH
Q
High Impedance
AI01447C
Figure 25. Top Sector Lock setup and hold timing
TSL tTHSL
tSHTL
S
C
D High Impedance Q
AI07439b
45/51
DC and AC parameters Figure 26. Output Timing
S tCH C tCLQV tCLQX Q tQLQH tQHQL D
ADDR.LSB IN
M25PE80
tCLQV tCLQX
tCL
tSHQZ
LSB OUT
AI01449e
Table 17.
Reset timings
Test conditions specified in Table 12 and Table 13
Symbol tRLRH(1)
Alt.
Parameter
Conditions
Min. 10
Typ.
Max.
Unit s
tRST Reset Pulse Width after any operation except for PW, PP, PE, SE and BE
30 300
s s
tRHSL
tREC Reset Recovery Time
After PW, PP, PE, SE and BE operations(1) Chip should have been deselected before Reset is deasserted 10
tSHRH
Chip Select High to Reset High
ns
1. Value guaranteed by characterization, not 100% tested in production.
Figure 27. Reset AC waveforms
S
tSHRH tRLRH
tRHSL
Reset
AI06808
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M25PE80
Package mechanical
11
Package mechanical
Figure 28. VFQFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead, 6x5mm, Package Outline
D D1
E E1
E2
e
b A A2 L D2
A1 A3
VFQFPN-01
1. Drawing is not to scale. 2. The circle in the top view of the package indicates the position of pin 1.
Table 18.
VFQFPN8 (MLP8) 8-lead Very thin Dual Flat Package No lead, 6x5mm, Package Mechanical Data
millimeters inches Max. 1.00 0.00 0.65 0.20 0.40 6.00 5.75 3.40 5.00 4.75 4.00 1.27 0.60 0.50 0.75 12 3.80 4.20 3.20 3.60 0.35 0.48 0.05 0.0256 0.0079 0.0157 0.2362 0.2264 0.1339 0.1969 0.1870 0.1575 0.0500 0.0236 0.0197 0.0295 12 0.1496 0.1654 0.1260 0.1417 0.0138 0.0189 Typ. 0.0335 0.0000 Min. Max. 0.0394 0.0020
Symbol Typ. A A1 A2 A3 b D D1 D2 E E1 E2 e L 0.85 Min.
47/51
Package mechanical
M25PE80
Figure 29. SO8 wide - 8 lead Plastic Small Outline, 208 mils body width, Package Outline
A2 B e D
A C CP
N
E
1
H A1 L
SO-b
1. Drawing is not to scale. 2. The circle in the top view of the package indicates the position of pin 1.
Table 19.
SO8 wide - 8 lead Plastic Small Outline, 208 mils body width, mechanical data
millimeters inches Max 2.03 0.10 0.25 1.78 0.35 0.20 - 0.45 - 0.10 5.15 5.20 1.27 - 7.70 0.50 0 8 5.35 5.40 - 8.10 0.80 10 8 0.050 0.203 0.205 - 0.303 0.020 0 0.008 0.014 - 0.004 Typ Min Max 0.080 0.010 0.070 0.018 - 0.004 0.211 0.213 - 0.319 0.031 10
Symbol Typ A A1 A2 B C CP D E e H L N Min
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M25PE80
Part numbering
12
Part numbering
Table 20.
Example:
Ordering information scheme
M25PE80 - V MP 6 T P
Device Type M25PE = Page-Erasable Serial Flash Memory
Device Function 80 = 8Mbit (1Mb x 8)
Operating Voltage V = VCC = 2.7 to 3.6V
Package MW = SO8 (208 mils width) MP = VFQFPN8 6x5mm (MLP8)
Device Grade 6 = Industrial: device tested with standard test flow over -40 to 85 C
Option blank = Standard Packing T = Tape and Reel Packing
Plating Technology P or G = ECOPACK(R) (RoHs compliant)
For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office. The category of Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label.
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Revision history
M25PE80
13
Revision history
Table 21.
Date 24-Nov-2004 07-Dec-2004
Document revision history
Version 0.1 0.2 First Issue. 4KB Software protection granularity extended to Sector 15. SO16W package removed, SO8W package added. End timing line of tSHQZ modified in Figure 26: Output Timing. Plating Technology options modified in Table 20: Ordering information scheme. Minor text changes. Tables 2 and 3 and Figure 5 for details on the software protection scheme. Lock Register programming sequence detailed in Section Write to Lock Register (WRLR). Sections An easy way to modify data, A fast way to modify data, Page Write (PW) and Page Program (PP), updated to explain when using Page Write and Page Program instructions. Bulk Erase cycle time (tBE), Page Write cycle time (tPW) and Page Program cycle time (tPP) updated in Table 16: AC Characteristics. Version number updated for internet. No document changes. Document status updated to Preliminary Data. Page Program cycle time, tPP, and Page Write Cycle Time (n Bytes), tPW, updated in Table 16: AC Characteristics. ICC3 modified in Table 15: DC Characteristics. tSLCH, tCHSL, tCHSH, tSHCH and tBE modified in Table 16: AC Characteristics. MLP package renamed. Under Plating Technology, Blank option removed. Note 3 to Table 16 modified. Address modified in Figure 6: Block Diagram. Note added to Figure 28 and Figure 29. Document status promoted from Preliminary Data to full Datasheet status. Don't care address bits modified in Note 1 (below Figure 11) , Note 1 (below Figure 12), Note 1 (below Figure 14) , Note 1 (below Figure 15), Note 1 (below Figure 17) and Note 1 (below Figure 18). Small text changes. Changes
10-May-2005
0.3
25-Jul-2005
0.4
24-Aug-2005 25-Aug-2005
1.0 2.0
22-Nov-2005
3.0
12-May-2006
4
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M25PE80
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